1. Field of the Invention
The present invention relates to a digital PLL circuit which generates a digital signal which is synchronous in phase with an input digital signal.
2. Description of the Related Art
FIG. 7 is a block diagram showing the arrangement of a conventional digital PLL circuit. The conventional digital PLL circuit includes a DPC (Digital Phase Comparator) 1, a loop filter 2, and a DCO (Digital Control Oscillator) 3 including a counter, which are connected to one another in the form of a closed loop.
In the conventional digital PLL circuit, the DPC 1 operates as follows: Whenever an input digital signal .phi..sub.in is supplied to the DPC 1, the latter 1 fetches the count value CNT (described later) of the counter in the DCO 3, and holds it, and outputs it as a multi-path phase difference signal PC. The loop filter 2 is made up of a digital low-pass filter for instance. That is, the loop filter 2 removes unwanted frequency components from the phase difference signals which are outputted by the DPC 1 one after another in the above-described manner, and outputs frequency control data N in multiple paths. In the DCO 3, the following operation is repeatedly carried out: That is, a master clock signal of a predetermined frequency f is counted, and whenever the count value CNT reaches the frequency control data N, the counter is reset. Hence, the count value CNT is cyclically increased and decreased at a frequency corresponding to the frequency control data N. FIG. 8 shows variations of the count value CNT. More specifically, FIG. 8A is for the case where a frequency control data N small in value is given; and FIG. 8B is for the case where a frequency control data N.sub.2 large in value is given. In any one of those cases, the count value CNT cyclically increases at a predetermined rate corresponding to the frequency f of the master clock signal, and the cycle period is proportional to the frequency control data N. The DCO 3 outputs a digital signal .phi..sub.o according to the count value CNT which is increased and decreased in the above-described manner.
The DPC 1 latches the output count value CNT of the DCO 3 which is outputted in multiple paths, with the aid of the input digital signal .phi..sub.in, and outputs it as the phase difference signal PC. In the case where the digital signal .phi..sub.o is liable to lag in phase, the count value CNT latched by the DPC 1 with the aid of the input digital signal .phi..sub.in (i.e., the output phase difference signal PC of the DPC 1) is decreased. As a result, the frequency control data N is decreased, and the digital signal .phi..sub.o is caused to lead in phase. On the other hand, in the case where the digital signal .phi..sub.o is liable to lead in phase, the count value CNT latched by the DPC 1 with the aid of the input digital signal .phi..sub.in is increased. As a result, the frequency control data N is increased, and the digital signal .phi..sub.o is caused to lag in phase. That is, feedback control is carried out. Hence, the counter in the DCO 3 performs the counting operation being synchronous in phase with the input digital signal .phi..sub.in, and according to the count value of the counter the digital signal .phi..sub.o synchronous in phase with the input digital signal .phi..sub.in is produced. The digital PLL circuit of this type has been disclosed, for instance, by Unexamined Japanese Patent Application (OPI) No. Hei. 4-68817.
The above-described digital PLL circuit suffers from a problem that it is difficult to increase its operating range. The problem is as described below:
First, in order to increase the frequency resolution of the digital PLL circuit, it is necessary to increase the frequency f of the master clock signal which is supplied to the counter in the DCO 3.
In order to increase the range of allowable frequencies of the input digital signal .phi..sub.in without sacrificing the frequency resolution, it is necessary to increase the frequency f of the master clock signal (hereinafter referred to as "a clock frequency f", when applicable) supplied to the counter in the to a maximum, and to increase the number of bits of the counter, thereby increasing the upper limit value of the count value; i.e., the upper limit value of the frequency control data N.
However, the range of clock frequencies with which the counter operates normally has the upper limit (hereinafter referred to as "a highest operating frequency", when applicable). Hence, it is not permitted to set the clock frequency f to higher than the highest operating frequency.
In general, if, in the counter, the number of bits is increased, then the highest operating frequency is lowered. Hence, the request for increasing the clock frequency f is not compatible with the request for increasing the number of bits of the counter.
If, in this case, the number of bits of the counter is increased with the clock frequency f decreased, then it is possible to increase the range of allowable frequencies of the input digital signal .phi..sub.in with which the digital PLL circuit may be synchronous in phase; however, the frequency resolution of the digital PLL circuit is lowered.
If, on the other hand, the number of bits of the counter is decreased with the clock frequency f increased, then the frequency resolution of the digital PLL circuit may be sufficiently high; however, it is impossible to decrease the lower limit value of the range of allowable frequencies of the input digital signal .phi..sub.in.
As is apparent from the above description, in order to increase the range of allowable frequencies of the input digital signal, the frequency resolution of the digital PLL circuit must be sacrificed therefor; and in order to obtain a satisfactory frequency resolution, the range of frequencies of the input digital signal must be sacrificed therefor. Hence, it is difficult to increase the operating range of the digital PLL circuit.
The conventional digital PLL circuit suffers from another problem in that the phase-to-digital conversion gain of the DPC 1 varies depending on the frequency control data N, whereby the PLL loop gain is changed. As a result, it is difficult to obtain a stable operation over a wide range of frequencies. The problem will be described in more detail.
First, as shown in FIG. 8A, when a frequency control data N.sub.1 is given, the count value CNT of the counter in the DCO 3 is cyclically increased and decreased with a frequency f.sub.1. In response to the input digital signal .phi..sub.in, the count value CNT (=M) at that time instant is latched by the DPC 1, and is outputted as the phase difference signal PC.
In this operation, M master clock signals (where M is the number of the master clock signals) of the frequency f are counted until the digital signal .phi..sub.in is inputted, and therefore the period of time is M/f which elapses from the time instant that the count value CNT starts to increase until the digital signal .phi..sub.in is inputted. On the other hand, the period of increase and decrease of the count value CNT is 1/f.sub.1, which corresponds to a phase angle of 2.pi.. Hence, the true phase difference between the digital signal .phi..sub.in and the count value CNT is as follows: EQU 2.pi.{(M/f)/(1/f.sub.1)}=2.pi.Mf.sub.1 /f
Next, as shown in FIG. 8B, when a frequency control data N.sub.2 (N.sub.2 &gt;N.sub.1) is given, the count value CNT of the counter in the DCO 3 is cyclically increased and decreased with a frequency f.sub.2 (f.sub.2 &lt;f.sub.1). In response to the input digital signal .phi..sub.in, similarly as in the above-described case, the count value M is latched by the DPC 1, and outputted as the phase difference signal PC.
In this case, similarly as in the above-described case, the period of time which elapses from the time instant that the count value CNT starts to increase until the digital signal .phi..sub.in is inputted is M/f. However, the period of increase and decrease of the count value CNT is 1/f.sub.2, which corresponds to a phase angle of 2.pi.. Hence, the phase difference between the digital signal .phi..sub.in and the count value CNT is 2.pi.(Mf.sub.2)/f, which is smaller than the above-described value 2.pi.Mf.sub.1 /f.
As is apparent from the above-description, the phase difference between the digital signal .phi..sub.in and the count value CNT is not determined by the count value CNT only which is latched by the DPC 1; and even if the count values CNT latched are the same, those count values CNT represent different phase differences depending on the frequency control data N. That is, in converting the phase difference into the digital signal, the gain depends on the frequency control data N.
If the phase-to-digital conversion gain changes in the above-described manner, then the PLL loop gain is varied, which gives rise to the above-described problem.